Memory module and memory system including the same

ABSTRACT

A memory module includes memory devices; data buffers suitable for receiving write data transferred from a memory controller and transmitting read data to the memory controller; a buffer control signal generation circuit suitable for generating buffer control signals for controlling the data buffers, by using a command transferred from the memory controller; a command delay circuit suitable for generating an effective command by delaying the command by a delay amount of the buffer control signal generation circuit in a read operation and a write operation; a data processing circuit suitable for processing write data transferred from the data buffers and transferring processed write data to the memory devices, and processing read data transferred from the memory devices and transferring processed read data to the data buffers, in response to the effective command; and a command buffer circuit suitable for transferring the effective command to the memory devices.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority under 35 U.S.C. § 119 to Korean PatentApplication No. 10-2017-0062760 filed on May 22, 2017, which isincorporated herein by reference in its entirety.

TECHNICAL FIELD

The present disclosure relates to a semiconductor device. Particularly,the present disclosure relates to a memory module and a memory systemincluding the same.

DISCUSSION OF THE RELATED ART

In recent years, as mobile communication terminals such as art phonesand tablet PCs have become popular, and the use of social networkservices (SNS), machine to machine (M2M) networks, and sensor networkshas increased, the amount, generation speed, and variety of data are allincreasing rapidly.

In order to process big data, not only the speed of memory devices isimportant, but also the storage capacities of the memory devices andmemory modules including them need to be very large.

SUMMARY

Various embodiments are directed to providing a technology for enablinga memory module to operate stably while increasing the capacity of thememory module.

In an embodiment, a memory module may include: a plurality of memorydevices; a plurality of data buffers suitable for receiving write datatransferred from a memory controller and transmitting read data to thememory controller; a buffer control signal generation circuit suitablefor generating buffer control signals for controlling the plurality ofdata buffers, based on a command transferred from the to memorycontroller; a command delay circuit suitable for generating an effectivecommand based on a delay of the command by a delay amount of the buffercontrol signal generation circuit in a read operation and a writeoperation; a data processing circuit suitable for processing write datatransferred from the plurality of data buffers and transferring theprocessed write data to the plurality of memory devices, and suitablefor processing read data transferred from the plurality of memorydevices and transferring the processed read data to the plurality ofdata buffers, in response to the effective command; and a command buffercircuit suitable for transferring the effective command to the pluralityof memory devices.

In an embodiment, a memory system may include: a memory module; and amemory controller suitable for transmitting a command, an address, andwrite data to the memory module, and suitable for receiving read datafrom the memory module, the memory module including a plurality ofmemory devices; a plurality of data buffers suitable for receiving thewrite data transferred from the memory controller and transmitting theread data to the memory controller; a buffer control signal generationcircuit suitable for generating buffer control signals for controllingthe plurality of data buffers, based on the command; a command delaycircuit suitable for generating an effective command based on a delay ofthe command by a delay amount of the buffer control signal generationcircuit in a read operation and a write operation; a data processingcircuit suitable for processing write data transferred from theplurality of data buffers and transferring the processed write data tothe plurality of memory devices, and suitable for processing read datatransferred from the plurality of memory devices and transferring theprocessed read data to the plurality of data buffers, in response to theeffective command; and a command buffer circuit suitable fortransferring the effective command to the plurality of memory devices.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagram illustrating a configuration of a memory system inaccordance with an embodiment.

FIG. 2 is a timing diagram for a read operation in a memory module 100in accordance with an embodiment.

FIG. 3 is a timing diagram for a write operation in the memory module100 in accordance with an embodiment.

FIG. 4 is a diagram illustrating a configuration of a memory system inaccordance with an embodiment.

FIG. 5 is a diagram illustrating a configuration of the modulecontroller 410 shown in FIG. 4.

FIG. 6 is a timing diagram for a read operation in a memory module 400in accordance with an embodiment.

FIG. 7 is a timing diagram for a write operation in the memory module400 in accordance with an embodiment.

DETAILED DESCRIPTION

Various embodiments will be described below in more detail withreference to the accompanying drawings. The present invention may,however, be embodied in different forms and should not be construed aslimited to the embodiments set forth herein. Rather, these embodimentsare provided so that this disclosure will be thorough and complete, andwill fully convey the scope of the present invention to those skilled inthe art. Throughout the disclosure, like reference numerals refer tolike parts throughout the various figures and embodiments of the presentinvention.

FIG. 1 is a diagram illustrating a configuration of a memory system inaccordance with an exemplary embodiment.

Referring to FIG. 1, the memory system may include a memory controller 1of a host and a memory module 100.

The memory controller 1 of the host may transmit a command CMD, anaddress ADD, and a clock CLK to the memory module 100 in order tocontrol the memory module 100, and may transmit and receive data DATA toand from the memory module 100. The memory controller 1 may be includedin a processor such as a CPU (central processing unit), a GPU (graphicprocessing unit) and an AP (application processor) or may exist in aseparate semiconductor chip outside the processor. The memory controller1 may be employed in various systems using the memory module 100, suchas a PC, a server system, and a mobile system.

The memory module 100 may include a register clock driver (RCD) 110,data buffers 120_0 to 120_7, and memory devices 130_0 to 130_7. Thememory module 100 shown in FIG. 1 is referred to as an load reduced dualin-line memory module (LRDIMM).

The register clock driver 110 may buffer the command CMD, the addressADD, and the clock CLK provided from the memory controller 1, andprovide them to the memory devices 130_0 to 130_7. The register dockdriver 110 may also provide the clock CLK to the data buffers 120_0 to120_7. In addition, the register clock driver 110 may processinformation on the command CMD and the address ADD, which is to beprovided for the data buffers 120_0 to 120_7, into the appropriate formfor a buffer communication bus BCOM<0:3>, and may provide the processedinformation to the data buffers 120_0 to 120_7 through the buffercommunication bus BCOM<0:3>.

The data buffers 120_0 to 120_7 may receive data DATA from the memorycontroller 1 and transfer data to the memory devices 130_0 to 130_7 in awrite operation, and may receive data DATA from the memory devices 130_0to 130_7 and transfer data to the memory controller 1 in a readoperation. Since the data buffers 120_0 to 120_7 in the memory module100 directly exchange data DATA with the memory controller 1, the databuffers 120_0 to 120_7 may receive, in a write operation, data DATA fromthe memory controller 1 at a time when a write latency (WL) elapses froma timing at which a to write command is applied from the memorycontroller 1. Further, in the read operation, the data buffers 120_0 to120_7 may transmit data DATA to the memory controller 1 at a time when aCAS latency (CL) elapses from a time at which a read command is appliedfrom the memory controller 1. Therefore, the data buffers 120_0 to 120_7may require information on an application time of the write command andan application time of the read command, and may be provided with theinformation on application times of the write, and read commands,through the buffer communication bus BCOM<0:3> from the register clockdriver 110. In addition, information for setting up the data buffers120_0 to 120_7 may be provided to the data buffers 120_0 to 120_7through the buffer communication bus BCOM<0:3> from the register clockdriver 110.

The memory devices 130_0 to 130_7 may operate based on the command CMD,the address ADD, and the clock CLK transferred from the register dockdriver 110 and may also operate by transmitting and receiving data DATAthrough the data buffers 120_0 to 120_7. Each of the memory devices130_0 to 130_7 may be one among various kinds of memories such as a DRAM(dynamic random access memory), an RRAM (resistive random accessmemory), a PRAM (phase-change random access memory), an FRAM(ferroelectric random access memory), and an MRAM (magnetic randomaccess memory), for instance.

In the drawing, DATA_INT may denote buses through which data istransmitted between the data buffers 120_0 to 120_7 and the memorydevices 130_0 to 130_7 in the memory module 100, CMD/ADD/CLK_INT maydenote a bus through which a command, an address, and a dock aretransmitted to the memory devices 130_0 to 130_7 from the register clockdriver 110 in the memory module 100, and CLK_INT may denote a busthrough which a clock is transmitted to the data buffers 120_0 to 120_7from the register dock driver 110 in the memory module 100.

FIG. 2 is a timing diagram for a read operation in which a read commandis transferred to the memory devices 130_0 to 130_7 and the data buffers120_0 to 120_7 in accordance with one exemplary embodiment.

In FIG. 2, CMD may denote a command which is transmitted to the registerclock driver 110 from the memory controller 1, and CMD_INT may denote acommand which is transmitted to the memory devices 130_0 to 130_7 fromthe register clock driver 110.

Referring to FIG. 2, at a time 201, a read command RD may be transmittedto the register dock driver 110 from the memory controller 1.

Then, at a time 203 when three clocks elapse from the time 201, theregister clock driver 110 may transfer the buffered read command RD tothe memory devices 130_0 to 130_7. Further, at the same time 203, theregister clock driver 110 may transfer a read command changed into theform of buffer control signals to be transferred through the buffercommunication bus BCOM<0:3>, to the data buffers 120_0 to 120_7. Amongthe buffer control signals to be transferred through the buffercommunication bus BCOM<0:3>, RD may denote a buffer control signalindicating that the read command has been applied, and DATO may denote abuffer control signal indicating selected memory banks, and PAR maydenote a buffer control signal instructing a parity check for the readcommand and data.

Referring to FIG. 2 the register clock driver 110 transfers the readcommand notifying that the read operation has been instructed from thememory controller 1, to the memory devices 130_0 to 130_7 and the databuffers 120_0 to 120_7 at the same time 203 according to one exemplaryembodiment. In the read operation, the notice that the read command hasbeen applied may be transferred to the memory devices 130_0 to 130_7 andthe data buffers 120_0 to 120_7 at the same time according to oneexemplary embodiment. One reason for this embodiment is as follows: whenthe read latency of the memory devices 130_0 to 130_7 and the readlatency of the data buffers 120_0 to 120_7 match each other, a time atwhich data is outputted from the memory devices 130_0 to 130_7 and atime at which the data buffers 120_0 to 120_7 buffer the data outputtedfrom the memory devices 130_0 to 130_7 and transfer it to the memorycontroller 1 would not likely mismatch each other.

FIG. 3 is a timing diagram for a write operation in which a writecommand is transferred to the memory devices 130_0 to 130_7 and the databuffers 120_0 to 120_7 in accordance with one exemplary embodiment.

Referring to FIG. 3, at a time 301, a write command WT may betransmitted to the register clock driver 110 from the memory controller1.

Then, at a time 303 when three docks elapse from the time 301, theregister dock driver 110 may transfer the buffered write command WT tothe memory devices 130_0 to 130_7. Further, at the same time 303, theregister clock driver 110 may transfer a write command changed in theform of buffer control signals to be transferred through the buffercommunication bus BCOM<0:3>, to the data buffers 120_0 to 120_7. Amongthe buffer control signals to be transferred through the buffercommunication bus BCOM<0:3>, WT may denote a buffer control signalindicating that the write command has been applied, and DAT0 may denotea buffer control signal indicating selected memory banks, and PAR maydenote a buffer control signal instructing a parity check for the writecommand and data.

Referring to FIG. 3, the register clock driver 110 transfers the writecommand notifying that the write operation has been instructed from thememory controller 1, to the memory devices 130_0 to 130_7 and the databuffers 120_0 to 120_7 at the same time 303 according to one exemplaryembodiment. In the write operation, similarly to the read operation, thenotice that the write command has been applied is transferred to thememory devices 130_0 to 130_7 and the data buffers 120_0 to 120_7 at thesame time according to one embodiment. One reason for this embodiment isas follows: when the write latency of the memory devices 130_0 to 130_7and the write latency of the data buffers 120_0 to 120_7 match eachother, a time at which the data buffers 120_0 to 120_7 buffer datatransferred from the memory controller 1 and transfer the buffered datato the memory devices 130_0 to 130_7 and a time at which the memorydevices 130_0 to 130_7 receive the data transferred from the databuffers 120_0 to 120_7 would not likely mismatch each other.

FIG. 4 is a diagram illustrating a configuration of a memory system inaccordance with one exemplary embodiment.

Referring to FIG. 4, the memory system may include a memory controller 4of a host and a memory module 400.

The memory controller 4 of the host may transmit a command CMD, anaddress ADD, and a dock CL K to the memory module 400 in order tocontrol the memory module 400, and may transmit and receive data DATA toand from the memory module 400. The memory controller 4 may be includedin a processor such as a CPU (central processing unit), a GPU (graphicprocessing unit), and an AP (application processor) or may exist in aseparate semiconductor chip outside the processor. The memory controller4 may be employed in various systems using the memory module 400, suchas a PC, a server system, and a mobile system.

The memory module 400 may include a module controller 410, data buffers420_0 to 420_7, and memory devices 430_0 to 430_7.

Each of the memory devices 430_0 to 430_7 may have a substantially largecapacity. To this end, each of the memory devices 430_0 to 430_7 mayinclude a plurality of memory chips which are stacked according to oneembodiment. For example, each of the memory devices 430_0 to 430_7 mayinclude eight memory chips, and the entire memory devices 430_0 to 430_7of the memory module 400 may include 64 memory chips. In the case wherea plurality of memory chips are stacked to increase the capacity of thememory devices 430_0 to 430_7, since loading increases and routing of alarge number of signals becomes difficult, the latencies of the memorydevices 430_0 to 430_7 tend to increase, and a number of errors tend tooccur during write and read operations. Each of the memory devices 430_0to 430_7 may be one among various kinds of memories such as a DRAM(dynamic random access memory), an RRAM (resistive random accessmemory), a PRAM phase-change random access memory), an FRAM(ferroelectric random access memory), and an MRAM (magnetic randomaccess memory),

The module controller 410 may buffer the command CMD, the address ADD,and the clock CLK provided from the memory controller 4, and providethem to the memory devices 430_0 to 430_7. The module controller 410 mayalso provide the clock CLK to the data buffers 420_0 to 420_7. Inaddition, the module controller 410 may process information on thecommand CMD and the address ADD, which is to be provided for the databuffers 420_0 to 420_7, into the appropriate form for a buffercommunication bus BCOM<0:3>, and may provide the processed informationto the data buffers 420_0 to 420_7 through the buffer communication busBCOM<0:3>. The above-described operations of the module controller 410may be the same as the operations of the register clock driver 110.

Unlike the register clock driver 110, however, the module controller 410may perform the function of transferring data DATA between the databuffers 420_0 to 420_7 and the memory devices 430_0 to 430_7. In a writeoperation, the module controller 410 may generate an error correctioncode (ECC) by using write data transferred from the data buffers 420_0to 420_7. The module controller 410 may transmit the write data and theerror correction code to the memory devices 430_0 to 430_7 such that thewrite data and the error correction code may be written into the memorydevices 430_0 to 430_7. Moreover, in a read operation, the modulecontroller 410 may correct error in read data from the memory devices430_0 to 430_7 by using an error correction code read from the memorydevices 430_0 to 430_7, and may transmit error-corrected read data tothe data buffers 420_0 to 420_7. Therefore, data may be transmittedthrough an internal data bus DATA_INT1 between the data buffers 420_0 to420_7 and the module controller to 410, and data and an error correctioncode may be transmitted through an internal data bus DATA_INT2 betweenthe module controller 410 and the memory devices 430_0 to 430_7. By theerror correction code generating operation and the error correctingoperation of the module controller 410, it is possible to correct errorsthat tend to increase due to the expanded capacities and stacked memorychips in the memory devices 430_0 to 430_7.

In addition, in order to increase the data capacities of the memorydevices 430_0 to 430_7 the module controller 410 may perform operationsof compressing and decompressing data. For example, by compressing dataand transferring compressed data to the memory devices 430_0 to 430_7 ina write operation and by decompressing data read from the memory devices430_0 to 430_7 and transferring decompressed data to the data buffers420_0 to 420_7 in a read operation, it is possible to store an increasedamount of data in the memory devices 430_0 to 430_7.

Unlike the memory system of FIG. 2, in the memory system of FIG. 4, themodule controller 410 and the data buffers 420_0 to 420_7 may directlytransmit and receive data in read and write operations. Thus, the datatransmission and receiving timings of the module controller 410 may needto match the data transmission and receiving timings of the data buffers420_0 to 420_7 according to one embodiment.

FIG. 5 is a diagram illustrating a configuration of the modulecontroller 410 shown in FIG. 4 in accordance with one exemplaryembodiment.

Referring to FIG. 5, the module controller 410 may include a buffercontrol signal generation circuit 510, a command delay circuit 520, anaddress delay circuit 530, a command buffer circuit 540, an addressbuffer circuit 550, a clock buffer circuit 560, and a data processingcircuit 570.

The buffer control signal generation circuit 510 may generate buffercontrol signals for controlling the data buffers 420_0 to 420_7, thatis, signals to be loaded on the buffer communication bus BCOM<0:3>, byusing the command CMD and the address ADD. The buffer control signalgeneration circuit 510 may convert information that is necessary for theoperations of the data buffers 420_0 to 420_7 from the informationtransferred in the command CMD and the address ADD, into buffer controlsignals which conform to the protocol of the buffer communication busBCOM<0:3>. The buffer control signal generation circuit 510 may beinputted with the entire bits of the address ADD or may be inputted withpartial bits of the address ADD.

The command delay circuit 520 may generate an effective command CMD_EFFby delaying the command CMD by the delay amount of the buffer controlsignal generation circuit 510 in read and write operations. For example,if a delay of three clocks occurs for the buffer control signalgeneration circuit 510 to generate the buffer control signals by usingthe command CMD and the address ADD, the command delay circuit 520 maygenerate the effective command CMD_EFF by delaying the command CMD bythree clocks in the same manner. With respect to other commands than aread operation and a write operation, however, the command delay circuit520 may not delay the command CMD and may simply generate the effectivecommand CMD_EFF as the command CMD is e.g., without any delay). In otherwords, as for other commands than a read operation and a writeoperation, the delay value of the command delay circuit 520 may be setto 0. The command delay circuit 520 may distinguish a read operation anda write operation from the other operations based on the receivedcommand CMD.

The address delay circuit 530 may generate an effective address ADD_EFFby delaying the address ADD by the delay amount of the buffer controlsignal generation circuit 510 in read and write operations. With respectto commands other than a read operation and a write operation however,the, address delay circuit 530 may not delay the address ADD and maysimply generate the effective address ADD_EFF as the address ADD is. Inother words, the address delay circuit 530 may generate the effectiveaddress ADD_EFF by delaying or not delaying the address ADD in the samemanner as the command delay circuit 520 may or may not delay the commandCMD. A read/write signal RD/WT is a signal for the command delay circuit520 to notify the address delay circuit 530 of a read operation and awrite operation. Namely, the read/write signal RD/WT is a signal that isactivated in a read operation and a write operation.

The command buffer circuit 540 may buffer the effective command CMD_EFFand transfer the buffered command to the memory devices 430_0 to 430_7.The address buffer circuit 550 may buffer the effective address ADD_EFFand transfer the buffered address to the memory devices 430_0 to 430_7.The clock buffer circuit 560 may buffer the dock CLK transferred fromthe memory controller 4 and transfer the buffered dock to the memorydevices 430_0 to 430_7 and the data buffers 420_0 to 420_7. The commandbuffered by the command buffer circuit 540, the address buffered by theaddress buffer circuit 550, and the clock buffered by the clock buffercircuit 560 may be transferred to the memory devices 430_0 to 430_7through a bus CMD/ADD/CLK_INT. Also, the clock buffered by the clockbuffer circuit 560 may be transferred to the data buffers 420_0 to 420_7through a bus CLK_INT.

The data processing circuit 570 may include a first. serial-to-paralleland parallel-to-serial converting section 571, an error correction codegenerating section 572, an error correcting section 573, a compressingsection 574, a decompressing section 575, a selecting section 576, asecond serial-to-parallel and parallel-to-serial converting section 577,and a data processing control section 578.

The first serial-to-parallel and parallel-to-serial converting section571 may serial-to-parallel convert data DATA transferred from the databuffers 420_0 to 420_7 and transfer the converted data to the errorcorrection code generating section 572 in a write operation, and mayparallel-to-serial convert data DATA transferred from the errorcorrecting section 573 and transfer the converted data to the databuffers 420_0 to 420_7 in a read operation. This is to enable the errorcorrection code generating section 572 and the error correcting section573 to process data in parallel and thereby shorten the time requiredfor generating an error correction code ECC and correcting error.

The error correction code generation circuit 572 may generate the errorcorrection code ECC by using data DATA transferred from the firstserial-to-parallel and parallel-to-serial converting section 571, in thewrite operation. The error correcting section 573 may correct any errorin data DATA by using the error correction code ECC transferred from thesecond serial-to-parallel and parallel-to-serial converting section 577or the decompressing section 575, in the read operation.

The compressing section 574 may compress the data DATA and the errorcorrection code ECC and thereby decrease the numbers of bits thereof inthe write operation, In the drawing, data DATA′ and an error correctioncode ECC′ designate compressed counterparts of the data DATA and theerror correction code ECC, respectively. The decompressing section 575may decompress the data DATA′ and the error correction code ECC′ in theread operation.

The selecting section 576 is a component for selecting whether to usethe compressing section 574 and the decompressing section 575. In anembodiment where a compressing function is not used, the selectingsection 576 may electrically couple the error correction code generatingsection 572 and the error correcting section 573 with the secondserial-to-parallel and parallel-to-serial converting section 577. Inother words, the compressing section 574 and the decompressing section575 may be bypassed. In an embodiment where a compressing function isused, the selecting section 576 may electrically couple the compressingsection 574 and the decompressing section 575 with the secondserial-to-parallel and parallel-to-serial converting section 577.

The second serial-to-parallel and parallel-to-serial converting section577 may parallel-to-serial convert data and an error correction code inthe write operation, and may serial-to-parallel convert data and anerror correction code in the read operation. In other words, the secondserial-to-parallel and parallel-to-serial converting section 577 mayperform opposite operations to the first serial-to-parallel andparallel-to-serial converting section 571.

The data processing control section 578 may control the operations andthe operation timings of the components 571 to 577 in the dataprocessing circuit 570 in response to the effective command CMD_EFF. Inthe drawing, the symbol CTRL between the data processing control section578 and the components 571 to 577 indicates that the data processingcontrol section 578 controls the components 571 to 577. Since the timingcontrol operation of the data processing control section 578 is notimplemented in response to the command CMD but is implemented inresponse to the effective command CMD_EFF, the data processing timing ofthe data processing control section 578 and the data processing timingof the data buffers 420_0 to 420_7 may match each other. These two dataprocessing timings would unlikely mismatch each other because the databuffers 420_0 to 420_7 operate in response to control signals on thebuffer communication bus BCOM<0:3>, which have the same timinginformation as the effective command CMD_EFF.

While it is illustrated in FIG. 5 that the module controller 410includes the buffer control signal generation circuit 510, the commanddelay circuit 520, the address delay circuit 530, the command buffercircuit 540 the address buffer circuit 550, the clock buffer circuit560, and the data processing circuit 570, it is to be noted that somecomponents among them may be omitted depending on its design. Forexample, in the case where an error correcting operation is not needed,the error correction code generating section 573 and the errorcorrecting section 574 may be omitted in the data processing circuit570. Also, in the case where a data compressing operation is not needed,the compressing section 574, the decompressing section 575, and theselecting section 576 may be omitted in the data processing circuit 570.

Further, while it is illustrated in FIG. 5 that the buffer controlsignal generation circuit 510, the command delay circuit 520, theaddress delay circuit 530, the command buffer circuit 540, the addressbuffer circuit 550, the clock buffer circuit 560, and the dataprocessing circuit 570 are included in the module controller 410, it isto be noted that some components among them may be provided outside themodule controller 410. In addition each function block shown in FIG. 5(e.g., the delay circuits and sections) may include suitable circuitelements adapted to perform the functions as described. For instance,the command delay circuit 520 may include a hardware circuit adapted todelay the received command CMD and output the delayed command CMD_EFF.

FIG. 6 is a timing diagram for a read operation in which a read commandis transferred to the data processing circuit 570 and the data buffers420_0 to 420_7 in the memory module 400.

Referring to FIG. 6, at a time 601, a read command RD may be transmittedto the memory module 400 from the memory controller 4.

Then, at a time 603 when three docks elapse from the timing 601, thebuffer control signals generated by the buffer control signal generationcircuit 510, that is, buffer control signals notifying the applicationof the read command RD, may be transferred to the data buffers 420_0 to420_7 through the buffer communication bus BCOM<0:3>.

Also, at the same time 603, an effective read command RD_EFF generatedby the command delay circuit 520 may be transferred to the dataprocessing circuit 570.

Since the notice that the read command RD has been applied istransferred to the data buffers 420_0 to 420_7 and the data processingcircuit 570 at the same time, the data buffers 420_0 to 420_7 and thedata processing circuit 570 may transmit and receive data withoutexperiencing a mismatch in timing.

FIG. 7 is a timing diagram for a write operation in which a writecommand is transferred to the data processing circuit 570 and the databuffers 420_0 to 420_7 in the memory module 400.

Referring to FIG. 7, at a time 701, a write command WT may betransmitted to the memory module 400 from the memory controller 4.

Then, at a time 701 when three clocks elapse from the timing 703, thebuffer control signals generated by the buffer control signal generationcircuit 510, that buffer control signals notifying the application ofthe write command WT, may be transferred to the data buffers 420_0 to420_7 through the buffer communication bus BCOM<0:3>.

Also, at the same time 703, an effective write command WT_EFF generatedby the command delay circuit 520 may be transferred to the dataprocessing circuit 570.

Since the notice that the write command WT has been applied istransferred to the data buffers 420_0 to 420_7 and the data processingcircuit 570 at the same time, the data buffers 420_0 to 420_7 and thedata processing circuit 570 may transmit and receive data withoutexperiencing a mismatch in timing.

According to various embodiments, it is possible to enable a memorymodule to operate stably while increasing the capacity of the memorymodule.

Although various embodiments have been described for illustrativepurposes, it will be apparent to those skilled in the art that variouschanges and modifications may be made without departing from the spiritand scope of the invention as defined in the following claims.

What is claimed is:
 1. A memory module comprising: a plurality of memorydevices; a plurality of data buffers suitable for receiving write datatransferred from a memory controller and transmitting read data to thememory controller; and a module controller comprising: a buffer controlsignal generation circuit suitable for generating buffer control signalsfor controlling the plurality of data buffers, based on a commandtransferred from the memory controller; a command delay circuit suitablefor generating an effective command based on a delay of the command by adelay amount of the buffer control signal generation circuit in a readoperation and a write operation; a data processing circuit suitable forprocessing write data transferred from the plurality of data buffers andtransferring the processed write data to the plurality of memorydevices, and processing read data transferred from the plurality ofmemory devices and transferring the processed read data to the pluralityof data buffers, in response to the effective command; and a commandbuffer circuit suitable for transferring the effective command to theplurality of memory devices.
 2. The memory module according to claim 1,wherein the command delay circuit is suitable for generating theeffective command as the command is without delaying the command, in anoperation other than the read operation and the write operation.
 3. Thememory module according to claim 2, wherein the module controllerfurther comprises: an address delay circuit suitable for generating aneffective address based on a delay of an address transferred from thememory controller by the delay amount of the buffer control signalgeneration circuit in the read operation and the write operation; and anaddress buffer circuit suitable for transferring the effective addressto the plurality of memory devices.
 4. The memory module according toclaim 3, wherein the address delay circuit is suitable forgenerating-the effective address as the address is without delaying theaddress, in an operation other than the read operation and the writeoperation.
 5. The memory module according to claim 4, wherein the modulecontroller further comprises: a clock buffer circuit suitable fortransferring a clock transferred from the memory controller to theplurality of memory devices.
 6. The memory module according to claim 1,wherein the data processing circuit comprises: an error correction codegenerating section suitable for generating, based on the write datatransferred from the plurality of data buffers, an error correction codeto be stored together with the write data in the plurality of memorydevices, in the write operation; and an error correcting sectionsuitable for correcting an error in the read data read from theplurality of memory devices, based on an error correction code read fromthe plurality of memory devices, in the read operation.
 7. The memorymodule according to claim 6, wherein the data processing circuit furthercomprises: a compressing section suitable for compressing the write dataand the error correction code to be stored in the plurality of memorydevices, in the write operation; and a decompressing section suitablefor decompressing the read data and the error correction code read fromthe plurality of memory devices, in the read operation.
 8. The memorymodule according to claim 6, wherein the data processing circuit furthercomprises: a data processing control section suitable for controllingoperations of the error correction code generating section and the errorcorrecting section in response to the effective command.
 9. The memorymodule according to claim 1, wherein each of the plurality of memorydevices is a dynamic random access memory (DRAM), and wherein the memorymodule is a dual in-line memory module (DIMM) type.
 10. A memory systemcomprising: a memory module; and a memory controller suitable fortransmitting a command, an address, and write data to the memory module,and receiving read data from the memory module, the memory modulecomprising: a plurality of memory devices; a plurality of data bufferssuitable for receiving the write data transferred from the memorycontroller and transmitting the read data to the memory controller; anda module controller comprising: a buffer control signal generationcircuit suitable for generating buffer control signals for controllingthe plurality of data buffers, based on the command; a command delaycircuit suitable for generating an effective command based on a delay ofthe command by a delay amount of the buffer control signal generationcircuit in a read operation and a write operation; a data processingcircuit suitable for processing write data transferred from theplurality of data buffers and transferring the processed write data tothe plurality of memory devices, and processing read data transferredfrom the plurality of memory devices and transferring the processed readdata to the plurality of data buffers, in response to the effectivecommand; and a command buffer circuit suitable for transferring theeffective command to the plurality of memory devices.
 11. The memorysystem according to claim 10, wherein the command delay circuit issuitable for generating the effective command as the command is withoutdelaying the command, in an operation other than the read operation andthe write operation.
 12. The memory system according to claim 11,wherein the module controller further comprises: an address delaycircuit suitable for generating an effective address based on a delay ofan address transferred from the memory controller by the delay amount ofthe buffer control signal generation circuit in the read operation andthe write operation; and an address buffer circuit suitable fortransferring the effective address to the plurality of memory devices.13. The memory system according to claim 12, wherein the address delaycircuit is suitable for generating the effective address as the addressis without delaying the address, in an operation other than the readoperation and the write operation.
 14. The memory system according toclaim 13, wherein the module controller further comprises: a clockbuffer circuit suitable for transferring a clock transferred from thememory controller to the plurality of memory devices.
 15. The memorysystem according to claim 10, wherein the data processing circuitcomprises: an error correction code generating section suitable forgenerating, based on the write data transferred from the plurality ofdata buffers, an error correction code to be stored together with thewrite data in the plurality of memory devices, in the write operation;and an error correcting section suitable for correcting an error in theread data read from the plurality of memory devices, based on an errorcorrection code read from the plurality of memory devices, in the readoperation.
 16. The memory system according to claim 15, wherein the dataprocessing circuit further comprises: a compressing section suitable forcompressing the write data and the error correction code to be stored inthe plurality of memory devices, in the write operation; and adecompressing section suitable for decompressing the read data and theerror correction code read from the plurality of memory devices, in theread operation.
 17. The memory system according to claim 16, wherein thedata processing circuit further comprises: a data processing controlsection suitable for controlling operations of the error correction codegenerating section and the error correcting section in response to theeffective command.
 18. The memory system according to claim 10, whereineach of the plurality of memory devices is a dynamic random accessmemory (DRAM), and wherein the memory module is a dual in-line memorymodule (DIMM) type.